The present invention relates to integrated circuits, and, more particularly, to a reading device and associated methods for an integrated circuit memory. Integrated circuit memories include erasable programmable read only memories (EPROMS) and one-time programmable (OTP) type non-volatile electrically programmable memories, for example. The present invention reduces the read access time of a memory, particularly with respect to the time taken for the data stored in one or more memory cells to become available at an output.
The cells of a memory are usually organized in matrix form using bit lines and word lines. The bit lines are the conductors by which the state stored in a cell is read. Thus, when a memory cell is addressed in a read mode, the corresponding word line is selected and the corresponding bit line is connected to a reading device.
In general, it is not just one memory cell but several that are read for the reading of a memory word. Generally, all these cells forming a memory word belong to the same word line, and a respective bit line corresponds to each cell. In a read mode, each one of these bit lines is connected to a corresponding reading device, which are all identical.
Since the bit lines comprise a large number of cells, they are capacitive and resistive. The capacitance is a result of the sum of the individual capacitances due to the components themselves. The components include the cells, the selection transistors, and the topology of the bit lines. The resistance is because of the materials used, such as the contact resistances, the metallization and the internal resistances of the transistors of the cells.
For these reasons, the reading device usually comprises a precharging circuit to charge the equivalent capacitance of a bit line selected in a read mode to a determined precharging read voltage. Then, a current generation circuit sets up a current in the bit line. If the selected cell absorbs current, a voltage variation will be detected on the line. In the case of EPROM type memory cells, the reading device furthermore comprises a voltage limiter to limit the voltage of the bit lines to a level close to one volt to eliminate the risk of memory cells being programmed during the read access operations.
In addition, the reading is often based on a comparison between the current that flows in the cell selected in the read mode and the current that flows in a reference cell. For example, in the case of a EPROM type memory or OTP type memory, the two possible states of a storage cell are the blank state and the programmed state. The blank state is produced by erasing the cells using UV rays. The reference cells are all in the same known state, which is generally the blank state. In this state, the floating-gate transistor of the memory cell has a low threshold voltage of about 1.4 volts, for example. In the programmed state, this threshold voltage becomes higher, and may be equal to 5.5 volts, for example.
The principle of reading by comparison is based on the fact that the cell selected in the read mode is in an erased state. It can absorb as much current as the reference cell placed in the same bias conditions. If this cell is provided with only a fraction of this current, it will make the bit line voltage collapse, and this fact will be detected.
In practice, a read current generator injects a given read current Iref into the reference bit line associated with the reference cell, and it injects a fraction of this reference current (e.g., half or one third) into the data bit line associated with the cell to be read. A read differential amplifier receives a signal coming from the data bit line at the first differential input, and a signal coming from the reference bit line at the second differential input.
If the cell that is read is erased, it draws more current than the fraction of the reference current provided to it by the current generator. The first differential input is then drawn to a voltage U lower than the voltage Uref at the second input of the differential amplifier, and the output of the amplifier switches over in one direction. If, on the contrary, the cell that is read is programmed, it absorbs very low current or no current at all. The first differential input is then drawn to a voltage U higher than the voltage Uref at the second input of the differential amplifier, and the output of the amplifier switches over into the other direction.
Thus, a common reading device comprises a precharging circuit for each of the bit lines with limitation of the bit line voltage. The device also comprises a read current generator in the bit lines, and a read amplifier that provides the information at an output.
The precharging circuit is a current/voltage converter that fulfills three different functions. A first function supplies current to precharge the bit lines. A second function limits the bit line potential to a specified precharging read voltage, which eliminates the risks of programming. A third function supplies a signal to the amplifier with a voltage that varies strongly with the current on the associated bit line in the evaluation stage.
The reading device thus goes through several stages of operation. These stages include the starting up of the precharging circuits, the activation of the read current generators, the selection and precharging of the bit lines, and the selection of the word line (row decoding). The voltage levels perceived by the read amplifier are often close to VDD, and are related not to the state of the selected cell but to the precharging circuit.
At this time, the cell selected in the read mode may or may not absorb current. If current is absorbed, such as in the case of a blank or erased cell, this current is first given by the bit line capacitance and then by the associated read current generator. This absorption of current produces a large variation of voltage in the signal applied at the input to the differential amplifier. This causes the amplifier to switch over.
However, the output of the amplifier oscillates throughout the variations on the bit lines. This slows down the setting up of the real data at the output. In practice, the sequencing operations needed to start up the various circuits of the reading device and the parasitic oscillations of the amplifier lengthen the read access time. One and a half clock cycles are needed to obtain the output data element. In one example, there is a typical read access time of 80 nanoseconds, and a maximum read access time of 130 nanoseconds.
To avoid the problem of oscillations at the output of the amplifier, there are reading devices which use a latch instead of the read differential amplifier. However, it is then necessary to plan an additional external sequencing to provide the activation signal for this latch as a function of all the time constraints and as a function of the sensitivity of the latch. This activation signal often comes from a control unit using reference circuits known as dummy circuits. These circuits are sized to obtain sufficient latitude in the light of the worst cases of propagation.
An object of the invention is to provide a very fast access reading device for a memory using a differential amplifier. In the invention, it is sought to improve the read access time of a memory. In one practical example, a maximum read access time of 25 nanoseconds is obtained instead of the typical prior art time of 80 nanoseconds. In the prior art, the reading is slowed down because of the successive sequencing operations needed and the oscillation of the amplifier.
Another object of the present invention is to provide a reading device that does not have the above described drawbacks.
A reading device according to the present invention comprises a dissymmetrical (or asymmetrical) precharging circuit to bring the input of the amplifier associated with the selected data bit line to a voltage level higher than that of the input associated with the reference bit line during the precharging phase. Consequently, the output of the amplifier is brought into a given state. In the following evaluation phase, the output of the amplifier is confirmed in this state, or else it switches over into the complementary state depending on the state stored in the cell on the selected bit line.
According to the present invention, the data and reference bit lines are precharged to a precharging read voltage of nearly one volt. This precharging is done in combination with an asymmetrical precharging of the inputs of the amplifier.
The invention also relates to a method of reading in an integrated circuit memory, wherein the method preferably comprises a precharging phase to bring a data bit line to a precharging voltage. The data bit line comprises a memory cell to be read, and a reference bit line comprises a reference cell.
A phase of evaluation includes the building-up of a reference current in the reference bit line, and a fraction of this current is built-up in the data bit line. A voltage signal given by a current/voltage converter connected to the data bit line, and a voltage signal given by a current/voltage converter connected to the reference bit line is applied respectively as a data input and as a reference input to a differential amplifier.
In the precharging phase, asymmetrical precharging is activated making it possible to bring one of the differential amplifier inputs to a voltage level higher than that of the other differential amplifier input.